Comprehensive Simulation Study of Statistical Variability in 32nm SOI MOSFET

1. Abstract We have studied the statistical variability (SV) in thinbody silicon-on-insulator (TBSOI) MOSFETs with high-κ/metal gate stacks. We have considered the impact of the gate workfunction variation (WFV) in conjunction with random discrete dopants (RDD) and trapped interface charges. The simulations were carried with the Glasgow 3D ’atomistic’ simulator GARAND. Results for both threshold voltage and on current variability are presented. 2. Introduction Statistical variability (SV) in the MOSFET parameters, due to discrete charges and granularity of matter is a big challenge to nano-CMOS scaling and integration [1]. SV in devices degrades circuit and system performance, and increases the power dissipations in chips. SV in bulk MOSFETs is dominated by random discrete dopants (RDD) in the channel [2]. Fully depleted (FD) TBSOI devices, without channel doping, promise to reduce SV, as is crucial for further gate length reduction. However, with the introduction of highκ/metal gate technology at the 45nm technology generation, WFV associated with different gate grain orientations becomes an extremely important source of SV for gate-first process [3, 4]. We study the impact of WFV on the threshold voltage (VT) variability of a 32nm n-channel FD TBSOI transistor with high-κ/metal gate stack with various grain sizes (from 5 to 30 nm) and orientation, using 3D physical device simulations, on a statistical scale. Further, we compare the WFV-induced VT variability with that due to RDD, LER, and PBTI-induced trapped charges [5]. 3. Device Structure The investigated device is a 32nm physical gate length TBSOI template nMOSFET developed by the EU PULLNANO consortium. This device features a TiN metal gate with a high-κ dielectric with equivalent oxide thickness of 1.2nm, and silicon body thickness of 7nm. The background channel doping concentrations is 1.2 × 10 cm. The buried oxide (BOX) thickness is 20nm. All other device specifications are following the ITRS requirement. 4. Simulation Methodology The Glasgow 3D ‘atomistic’ device simulator has been used in this study on statistical samples of 1000 microscopically different, but macroscopically identical transistors. WFV arises from the different surface density in grains of different orientation [4], and is modeled in the simulator by creating a random metal gate grain pattern for each simulated device. Such a pattern is imported into the simulator following a procedure similar to that used previously to investigate polysilicon granularity [6]. We simulate two possible metal grain orientations in the gate, with 40% probability, for the grain orientation with a work function of 4.48eV, and 60% for the grain orientation with a work function of 4.68eV [3]. The modeling of RDD and LER follows a well-established procedure, the parameters for LER being 1.3nm RMS amplitude and 25nm correlation length. The PBTI-induced trapped charge sheet density (TCD) are chosen to be 1×10, 5×10, 1×10 cm representative of early, intermediate and later aging stages respectively, with the assumption that the charges are trapped at the Si/SiO2 interfaces [7]. 5. Results and Discussion VT extraction is based on sub-threshold current criterion of 1 μA/μm, at high drain bias VD=1V, and for the uniform, continuously doped device results in VT = 329 mV. Fig. 1 shows the dependency of σVT on the average grain diameter of the metal gate for two simulation scenarios – with and without RDD and LER.